1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly, to a Vcom line layout in a liquid crystal display having no gate PCB (printed circuit board) and FPC (flexible printed circuit).
2. Description of the Prior Art
A liquid crystal display, which has been developed as a substitute for CRT (cathode ray tube), can realize lightweight, thin thickness and low power consumption, so that it is in the spotlight as the next-generation image display device. Currently, various studies to improve the display performance of the liquid crystal display are conducted.
Generally, this liquid crystal display comprises: a liquid crystal panel as a substantial display element; gate and source PCBs (printed circuit boards) as driving circuits serving to apply a given signal to the liquid crystal panel; a FPC (flexible printed circuit) connecting the PCBs with each other; a TCP (top carrier package) or COF (chip on film) connecting the liquid crystal panel to PCBs and mounted with a driver IC; a backlight unit disposed below the liquid crystal panel and serving as a light source; and means for assembling the above elements.
Meanwhile, to reduce the cost and weight of the liquid crystal display, there was recently proposed a liquid crystal display structure in which a LOG (line-on-glass) is formed on the liquid crystal panel, particularly an array substrate of the liquid crystal panel, with omission of the gate PCB and the FPC, and this LOC is connected to the source PCB such that a given signal for driving the gate driver IC are supplied.
FIGS. 1 to 4 are top views showing liquid crystal displays according to the prior art. Specifically, FIG. 1 shows a structure having the gate PCB and the FPC, FIG. 2 shows a structure having no FPC, and FIG. 3 shows a structure having no the gate PCB and the FPC.
In FIGS. 1 to 3, the reference numeral 1 designates a source PCB, the reference numeral 2 designates a gate PCB, the reference numeral 3 designates a FPC, the reference numeral 4 designates source TCPs, the reference numeral 5 designates gate TCPs, the reference numeral 6 designates an array substrate, the reference numeral 7 designates a color filter substrate, the reference numeral 8 designates a display region, the reference numeral 9 designates a LOC, the reference numeral 10 designates a common line, and the reference numeral 11 designates transfers.
Referring to FIG. 2, in the case of the liquid crystal display having no FPC 3, the LOG is additionally formed on the array substrate 6 of the liquid crystal panel in order to transmit a driving signal to the gate driver IC. Examples of such a driving signal include gate low voltage, gate high voltage, STV, CPV, OE, CND, Vdd, common voltage signals and the like, in which the common voltage signal is a signal for transmitting common voltage to the color filter substrate.
Referring to FIG. 3, in the case of the liquid crystal display having no PCB 2 and FPC 3, the LOG 9 is additionally formed on the array substrate of the liquid crystal panel as in the liquid crystal display having no FPC. In this case, the LOG 9 is also formed between the gate TCPs 5. Moreover, in order to transmit a common signal to the transfers 11 formed at the upper and lower portions of the lift side of the liquid crystal panel, the common line 10 is formed.
However, in the prior liquid crystal display having no gate PCB and FPC, since the LOG that is additionally formed on the array substrate must be formed to have low resistance, but this requirement is restricted by a spatial problem so that the problem of screen quality is caused.
Namely, although the adjustment of resistance of the LOG is very critical to avoid the problem of screen quality of the liquid crystal display having no FPC, it is difficult to adjust the resistance of the LOG to a suitable level, due to the spatial restriction. For this reason, the problem of output of the gate driver IC can be caused, and thus, the problem of screen quality of the liquid crystal display can occur.
Particularly, in the case of the common line in the LOG line, if the transfers are formed on a gate pad region, there will be defined a region in which the common line will be formed. For this reason, other lines need to be formed on the remaining regions other than this common line region, and thus, the spatial restriction will be serious. In this case, the transfers are usually formed to have a size of 0.5-1.5 mm. In addition, since specifications of pin arrangements in the driver IC are limited, this problem will be more serious.